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Consider the following Statements \(\mathbf{A}\) and \(\mathbf{B}\) and identify the correct answer: [NEET 2024]
A. For a solar-cell, the \(I-V\) characteristics lies in the IV quadrant of the given graph.
B. In a reverse-biased pn junction diode, the current measured in \((\mu \mathrm{A})\), is due to majority charge carriers.
(d) A : Solar cell characteristics
B : In a reverse-bias \(p-n\) junction diode, the current measured in \((\mu \mathrm{A})\), is due to minority charge carrier.
A logic circuit provides the output \(Y\) as per the following truth table:
\(
\begin{array}{|c|c|c|}
\hline A & B & Y \\
\hline 0 & 0 & 1 \\
\hline 0 & 1 & 0 \\
1 & 0 & 1 \\
1 & 1 & 0 \\
\hline
\end{array}
\)
The expression for the output \(Y\) is : [NEET 2024]
(b) \(Y=\bar{A} \cdot \bar{B}+A \bar{B}=\bar{B} (\bar{A} + A)=\bar{B}\)
The output \((Y)\) of the given logic gate is similar to the output of an/a: [NEET 2024]
(c) AND gate
\(
\begin{aligned}
Y & =\overline{\bar{A}+\bar{B}} \\
& =\bar{\bar{A}} \cdot \bar{\bar{B}}=A \cdot B
\end{aligned}
\)
Choose the correct circuit which can achieve the bridge balance : [NEET 2024]
(d) To Balance Bridge
\(\frac{P}{Q}=\frac{R}{S}\)
Here
\(
\begin{gathered}
P=10 \Omega \\
Q=10 \Omega \\
R=15 \Omega \\
S=5+R_{\text {diode }}
\end{gathered}
\)
The diode can conduct and have resistance \(R_D=10 \Omega\) because diode have dynamic resistance. In that case bridge will be balanced.
A solar cell is a: [NEET 2024]
(c) A solar cell, also known as a photovoltaic cell, is a type of diode that converts light into electricity using the photovoltaic effect. It’s different from a forward-biased Zener diode (which is a voltage regulator) or a light-emitting diode (which converts electricity into light), and it doesn’t require external biasing like some photodiodes.
Which input \((A, B)\)-output \((Y)\) combination correctly represents the given logic circuit? [NEET 2024]
(b) For \(\mathrm{A}=1, \mathrm{~B}=1\) : Both AND gates output 1 , so \(\mathrm{Y}=1\).
For \(\mathrm{A}=0, \mathrm{~B}=1\) : The first AND gate outputs 0 , but the second AND gate outputs 1 , so \(\mathrm{Y}=1\).
For \(\mathrm{A}=1, \mathrm{~B}=0\) : The first AND gate outputs 1 , but the second AND gate outputs 0 , so \(\mathrm{Y}=1\).
For \(\mathrm{A}=0, \mathrm{~B}=0\) : Both AND gates output 0 , so \(\mathrm{Y}=0\).
Zener diode works: [NEET 2024]
(d) A Zener diode works as a voltage regulator in reverse bias and behaves as a simple pn junction diode in forward bias. In other words, a Zener diode is primarily designed to be used in reverse bias, where it regulates voltage by maintaining a constant voltage across it once the reverse voltage reaches its breakdown voltage. However, in forward bias, it behaves like a regular diode, allowing current to flow in one direction.
The \(I-V\) characteristics shown below are exhibited by a: [NEET 2024]
(d) The I-V characteristics of solar cell is
When the output of an OR gate is applied as input to a NOT gate, then the combination acts as a: [NEET 2024]
(b) When the output of an OR gate is applied as input to a NOT gate, the combination acts as a NOR gate.
The output \(Y\) for the inputs \(A\) and \(B\) of the given logic circuit is: [NEET 2024]
(c) \(Y=\overline{\bar{A} \bar{B}}=A+B\) (OR Gate)
A full wave rectifier circuit consists of two p-n junction diodes, a centre-tapped transformer, capacitor and a load resistance. Which of these components remove the ac ripple from the rectified output? [NEET 2023]
(d)Â The component that removes the AC ripple from the rectified output in a full wave rectifier circuit is the capacitor.
Explanation: A capacitor acts as a filter, storing energy during the peaks of the rectified voltage and releasing it during the troughs, thus smoothing out the voltage fluctuations and reducing the ripple.
Given below are two statements:
Statement I: Photovoltaic devices can convert optical radiation into electricity.
Statement II: Zener diode is designed to operate under reverse bias in breakdown region.
In the light of the above statements, choose the most appropriate answer from the options given below : [NEET 2023]
(d) Statement I: Photocell/solar cell convert light energy into electric energy/current.
Statement II : We use Zener diode in reverse-bias condition, when the reverse-bias voltage is more than breakdown voltage, it act as stablizer.
For the following logic gate, the truth table is: [NEET 2023]
(c)
\(
\begin{aligned}
& Y=\overline{\overline{\mathrm{A}} \cdot \overline{\mathrm{~B}}}=\overline{\overline{\mathrm{A}}}+\overline{\overline{\mathrm{B}}} \\
& =(\mathrm{A}+\mathrm{B}) \text { OR Gate }
\end{aligned}
\)
The given circuit is equivalent to: [NEET 2023]
(d) \(Y= \overline{\bar{A}+\bar{B}}=A \cdot B\) which is an AND gate.
A p-type extrinsic semiconductor is obtained when Germanium is doped with: [NEET 2023]
(d) A p-type extrinsic semiconductor is obtained when Germanium is doped with boron (a trivalent impurity).
On the basis of electrical conductivity, which one of the following material has the smallest resistivity? [NEET 2023]
(b)Â Electrical conductivity is a measure of a material’s ability to conduct an electric current. The higher the conductivity, the lower the resistivity. So, if we are looking for the material with the smallest resistivity, we are looking for the material with the highest electrical conductivity.
Among the options given, silver (Option b) is known to have the highest electrical conductivity and thus, the smallest resistivity. Germanium (Option a) and silicon (Option d) are semiconductors, meaning they have moderate conductivity that can be manipulated, while glass (Option c) is generally a poor conductor, or an insulator. Therefore, silver is the correct answer.
In half-wave rectification, if the input frequency is 60 Hz , the output frequency will be: [NEET 2022]
(d) In half-wave rectification, if the input frequency is 60 Hz , the output frequency will also be 60 Hz . A half-wave rectifier only allows one half-cycle of the AC input to pass, so the output frequency remains the same as the input frequency.
As the temperature increases, the electrical resistance: [NEET 2022]
(d)Â The resistance increases for conductors but decreases for semiconductors as temperature increases. This is because the increase in temperature causes more collisions between electrons and atoms in conductors, increasing resistance. In semiconductors, more electrons gain energy and become available to carry current, reducing resistance.
Elaboration:
Conductors:
In conductors, increased temperature leads to more atomic vibrations, which hinders the flow of electrons, increasing resistance.
Semiconductors:
In semiconductors, higher temperatures provide more electrons with enough energy to move to the conduction band, increasing conductivity and reducing resistance.Â
In the given circuits \((a),(b)\), and \((c)\), the potential drop across the two \(p-n\) junctions is equal in: [NEET 2022]
(a)Â Potential drops across the p-n junctions will be same if either both junctions are forward biased or both junction are reverse biased.
In figure (a) and (c), both junctions are forward biased therefore both have same potential.
In figure (b) first junction is forward biased and the second junction is reverse biased, so both junctions have different potential difference.
The truth table for the given logic circuit is: [NEET 2022]
(d)
\(
\begin{aligned}
& C=(\overline{A \cdot B}) \cdot(\overline{\bar{A} \cdot B}) \\
& \Rightarrow C=\overline{A \cdot B+\bar{A} \cdot B} \\
& \Rightarrow C=\overline{(A+\bar{A}) B} \\
& \Rightarrow C=\bar{B}
\end{aligned}
\)
The output of the logic circuit shown is equivalent to a/an: [NEET 2022]
(a) \(\begin{aligned} y & =\overline{\overline{A+B}} \\ y & =A+B\end{aligned}\) which is an OR gate.
The circuit represents a full-wave bridge rectifier when switch \(S\) is open. The output voltage \(\left(\mathrm{V}_0\right)\) pattern across \(R_L\) when \(S\) is closed: [NEET 2022]
(a) When Switch S is open, basically the circuit behaves as a full-wave rectifier.
When S is closed, D5 turns on during the negative half of the input signal and the output voltage across load \(R_L\) = 0 V. During the positive half cycle, D5 is OFF and positive half cycle will appear across the load \(R_L\). Hence option a is correct.
The incorrect statement about the property of a Zener diode is: [NEET 2022]
(c) Zener diode is special-purpose p-n junction diode, which is generally operated in reverse bias for its operation of voltage regulation. It is a heavily doped p-n junction. Due to the large doping concentration depletion width is narrower.
Identify the equivalent logic gate represented by the circuit given below: [NEET 2022]
(a) The given circuit clearly indicates that the bulb will glow when either of the switches are closed.
The corresponding truth table will be
\(
\begin{array}{|c|c|c|}
\hline \text { Input A } & \text { Input B } & \text { Output } \mathrm{Y} \\
\hline 0 & 0 & 0 \\
\hline 0 & 1 & 1 \\
\hline 1 & 0 & 1 \\
\hline 1 & 1 & 1 \\
\hline
\end{array}
\)
This suggests that it will correspond to OR gate.
The electron concentration in an n-type semiconductor is the same as the hole concentration in a p-type semiconductor. An external field (electric) is applied across each of them. Compare the currents in them. [NEET 2021]
(a)
\(
\begin{aligned}
&\text { The current through a semiconductor is }\\
&\begin{aligned}
& \mathrm{I}=\mathrm{neAv}_{\mathrm{d}} \\
& \mathrm{I}=\mathrm{neA} \mu \mathrm{E} \quad\left(\text { as } \mathrm{v}_{\mathrm{d}}=\mu \mathrm{E}\right) \\
& \frac{I_n}{I_p}=\frac{n_e e A \mu_e E}{n_h e A \mu_h E} \\
& \frac{I_n}{I_p}=\frac{\mu_e}{\mu_h} \\
& \because \mu_{\mathrm{e}}>\mu_{\mathrm{h}} \\
& \Rightarrow I_n>I_p
\end{aligned}
\end{aligned}
\)
Given below are two statements:
Statement A: Zener diode is connected in reverse bias when used as a voltage regulator.
Statement B: The potential barrier of p-n junction lies between 0.2V to 0.3V. [NEET 2021]
(a) Statement A: A Zener diode is always connected in reverse bias to use it as a voltage regulator.
Explanation: A Zener diode is specifically designed to operate in reverse bias. When connected in reverse bias, it maintains a constant output voltage (known as the Zener voltage) across its terminals, even when the input voltage varies. This property makes it ideal for use in voltage regulation applications. Therefore, this statement is True.
Statement B: The potential barrier of a p-n junction lies between 0.1 to 0.3 V, approximately.
Explanation: The potential barrier of a p-n junction is typically in the range of 0.6 to 0.7 volts for silicon diodes, and can be higher for other semiconductor materials. The range of 0.1 to 0.3 volts is not accurate for \(p-n\) junctions. Therefore, this statement is False.
For the given circuit, the input digital signals are applied at the terminals \(A, B\) and \(C\). What would be the output at terminal \(Y\)? [NEET 2020]
(c)
\(
\begin{aligned}
& Y=A B+\overline{B C} \\
& =A B+\bar{B}+\bar{C}=B+\bar{B}+A+\bar{B}+\bar{C}=1+A+\bar{B}+\bar{C}=1
\end{aligned}
\)
For the logic circuit shown, the truth table is: [NEET 2020]
(c) \(Y=\overline{\bar{A}+\bar{B}}=\overline{\overline{A . B}}=\text { A.B }\)
The increase in the width of the depletion region in a p-n junction diode is due to: [NEET 2020]
(a) Reverse bias only.
Explanation:
In a p-n junction diode, reverse bias causes the majority charge carriers (holes in the p-type region and electrons in the n-type region) to be pulled away from the junction, resulting in an increase in the width of the depletion region.
Forward bias, on the other hand, decreases the width of the depletion region by allowing charge carriers to flow across the junction.
The solids which have the negative temperature coefficient of resistance are: [NEET 2020]
(c) The answer is insulators and semiconductors. Metals are excellent conductors, while insulators do not allow electrons to flow easily, and semiconductors have conductivity between the two. For metals temperature coefficient of resistance is positive while for insulators and semiconductors, temperature coefficient of resistance is negative
Out of the following which one is a forward-biased diode? [NEET 2020]
(d) For forward biasing potential of \(p\) type is greater than potential of \(n\) type junction.
Which of the following gate is called the universal gate? [NEET 2020]
(c) A Universal Gate is a gate by which every other gate can be realized.
AND, OR, NOT, etc. are basic gates.
NAND, NOR, etc. are the universal gate.
That means we can implement any logic function using NAND and NOR gates without the need of AND, OR, or NOT gates.
An intrinsic semiconductor is converted into an \(n\)-type extrinsic semiconductor by doping it with: [NEET 2020]
(a) To create N-type semiconductor, intrinsic semiconductor is doped by pentavalent impurity (Phosphorus)
For a p-type semiconductor, which of the following statements is true? [NEET 2019]
(c) Holes are the majority carriers and trivalent atoms are the dopants.
The correct Boolean operation represented by the circuit diagram given above is: [NEET 2019]
(d)
\(
\begin{array}{|l|l|l|}
\hline A & B & Y \\
\hline 0 & 0 & 1 \\
\hline 0 & 1 & 1 \\
\hline 1 & 0 & 1 \\
\hline 1 & 1 & 0 \\
\hline
\end{array}
\)
This is the truth table of an NAND gate.
An LED is constructed from a p-n junction diode using GaAsP. The energy gap is 1.9 eV. The wavelength of the light emitted will be equal to: [NEET 2019]
(b) Planck’s constant: \(h=6.626 \times 10^{-34} \mathrm{~J} \mathrm{~s}\)
Speed of light: \(c=3 \times 10^8 \mathrm{~m} / \mathrm{s}\)
Conversion factor: \(1 \mathrm{eV}=1.602 \times 10^{-19} \mathrm{~J}\)
Relationship between energy and wavelength: \(E=h \frac{c}{\lambda}\)
\(
\begin{aligned}
& E_g=1.9 \mathrm{eV} \times 1.602 \times 10^{-19} \mathrm{~J} / \mathrm{eV} \\
& E_g=3.0438 \times 10^{-19} \mathrm{~J}
\end{aligned}
\)
\(
\begin{aligned}
& \lambda=\frac{h c}{E_g} \\
& \lambda=\frac{\left(6.626 \times 10^{-34} \mathrm{~J} \mathrm{~s}\right)\left(3 \times 10^8 \mathrm{~m} / \mathrm{s}\right)}{3.0438 \times 10^{-19} \mathrm{~J}} \\
& \lambda=6.539 \times 10^{-7} \mathrm{~m} \\
& \lambda \approx 654 \times 10^{-9} \mathrm{~m} \\
& \lambda=654 \mathrm{~nm}
\end{aligned}
\)
The wavelength of the emitted light is 654 nm.
The circuit diagram shown here corresponds to the logic gate: [NEET 2019]
(A)
\(
\begin{array}{|c|c|c|}
\hline \text { A } & {B} & f{Y} \\
\hline 0 & 0 & 1 \\
\hline 1 & 0 & 0 \\
\hline 0 & 1 & 0 \\
\hline 1 & 1 & 0 \\
\hline
\end{array}
\)
This is truth table of a NOR gate.
In the combination of the following gates, the output \(Y\) can be written in terms of inputs \(A\) and \(B\) as: [NEET 2018]
(b) \(Y=(A \cdot \bar{B}+\bar{A} \cdot B)\)
In a p-n junction diode, the change in temperature due to heating: [NEET 2018]
(d)Â The correct answer is affects the overall V-I characteristics of a p-n junction.
Explanation:
When a p-n junction diode is heated, the number of free charge carriers (electron-hole pairs) increases. This increase in charge carriers affects both the forward and reverse bias characteristics of the diode. The change in temperature influences the resistance of the diode, leading to a shift in the V-I (voltage-current) curve.
Which one of the following represents forward biased circuit? [NEET 2017]
(a) In forward bias, the p-type semiconductor is at a higher potential w.r.t. n -n-type semiconductor.
The given electrical network is equivalent to: [NEET 2017]
(b) \(Y=\overline{A+B}\)
Which one of the following represents the forward bias diode? [NEET 2017]
(d) In forward bias, the p-type semiconductor is at a higher potential w.r.t. n -n-type semiconductor.
The given circuit has two ideal diodes connected as shown in the figure below. The current flowing through the resistance \(R_1\) will be {NEET 2016]
(a) Current will not flow through \(D_1\) as it is reverse biased. Current will flow through cell, \(R_1, D_2\) and \(R_3\).
\(
\therefore i=\frac{10}{2+2}=2.5 A
\)
To get output 1 for the following circuit, the correct choice for the input is [NEET 2016, 2012, 2010]
(c) \(Y=(A+B) C=1\)
What is the output \(Y\) in the following circuit, when all the three inputs \(A, B\), and \(C\) are first 0 and then 1? [NEET 2016]
(c)Â
\(
Y=\overline{(A B) C}
\)
\(
\begin{aligned}
& \text { for } A=B=C=0, y=1 \\
& \text { for } A=B=C=1, y=0
\end{aligned}
\)
Consider the junction diode as an ideal. The value of current flowing through \(A B\) is: [NEET 2016]
(a) For an ideal diode, potential drop across diode is zero. Since the current flows from higher potential to lower potential, the direction of a current will be from \(A\) to \(B\).
Current in the diode, \(I=\frac{\Delta V}{R}\)
\(
\Rightarrow I=\frac{V_A-V_B}{R}=\frac{4-(-6)}{1000}=\frac{10}{1000}=10^{-2} \mathrm{~A}
\)
In the given figure, a diode \(D\) is connected to an external resistance \(R=100 \Omega\) and an EMF of 3.5 V. If the barrier potential developed across the diode is 0.5 V, the current in the circuit will be: [NEET 2015]
(d) The potential difference across the resistance \(R\) is
\(
V=3.5 \mathrm{~V}-0.5 \mathrm{~V}=3 \mathrm{~V}
\)
By Ohm’s law,
The current in the circuit is
\(
I=\frac{V}{R}=\frac{3 \mathrm{~V}}{100 \Omega}=3 \times 10^{-2} \mathrm{~A}=30 \times 10^{-3} \mathrm{~A}=30 \mathrm{~mA}
\)
If in a p-n junction, a square input signal of 10 V is applied as shown, [NEET 2015]
then the output across \(R_L\) will be:
(d) Here P-N junction diode rectifies half of the ac wave, i.e., acts as half half-wave rectifier. During the positive half cycle
Diode \(\rightarrow\) forward biased output across will be
During – ve half cycle Diode \(\rightarrow\) reverse biased output will be 0V as (current across \(R_L\)=0 and hence no output voltage).
Which logic gate is represented by the following combination of logic gates? [NEET 2015]
(c)
\(
\begin{aligned}
&Y=\overline{\bar{A}+\bar{B}}=\overline{\bar{A}} \cdot \overline{\bar{B}}=A \cdot B\\
&\text { Thus, the combination represents AND gate. }
\end{aligned}
\)
The given graph represents the V-I characteristic for a semiconductor device. [NEET 2014]
Which of the following statement is correct?
(a) The \(V-I\) characteristic for a solar cell is as shown the figure.
The barrier potential of a p-n junction depends on: [NEET 2014]
(a) type of semiconductor material
(b) amount of doping
(c) temperature
Which one of the following is correct?
(d) The barrier potential depends on type of semiconductor (For \(\mathrm{Si}, V_b=0.7 \mathrm{~V}\) and for Ge, \(V_b=0.3 \mathrm{~V}\) ), amount of doping and also on the temperature.
In an n-type semiconductor, which of the following statement is true? [NEET 2013]
(b) In an n-type semiconductor, electrons are the majority charge carriers and holes are the minority charge carriers, and pentavalent atoms are dopants.
The output \((X)\) of the logic circuit shown in the figure will be: [NEET 2013]
(b) The output of the given logic circuit is
\(
X=\overline{\overline{A . B}}=A . B
\)
The output from a NAND gate is divided into two in parallel and fed to another NAND gate. The resulting gate is a: [AIPMT 2013]
(a) The output of the given logic gate is
\(
C=\overline{\overline{A B}}=A \cdot B
\)
Hence, the resulting gate is a AND gate.
In an unbiased p-n junction, holes diffuse from the \(p\)-regions to \(n\)-regions because of: [AIPMT 2013]
(b) \(\text { The higher hole concentration is in } p \text {-region than that in } n \text {-region. }\)
Two ideal diodes are connected to a battery as shown in the circuit. The current supplied by the battery is: [AIPMT 2012]
(d) In the given circuit the upper diode \(D_1\) is forward biased and the lower diode \(D_2\) is reverse biased. So, the current supplied by the battery is
\(
I=\frac{5 \mathrm{~V}}{10 \Omega}=\frac{1}{2} \mathrm{~A}=0.5 \mathrm{~A}
\)
C and Si both have the same lattice structure, having 4 bonding electrons in each. However, C is an insulator whereas Si is an intrinsic semiconductor. This is because: [AIPMT 2012]
(c)
\(
\begin{aligned}
&\text { The electronic configuration of Carbon (C) and Silicon (Si) is given by }\\
&\begin{aligned}
& { }_6 \mathrm{C}^{12}=2,4 (1 s^2 2 s^2 2 p^2) \\
& { }_{14} \mathrm{Si}^{28}=2,8,4 (1 s^2 2 s^2 2 p^6 3 s^2 3 p^2)
\end{aligned}
\end{aligned}
\)
Hence, the four bonding electrons of C and Si respectively lie in second and third orbit.
The figure shows a logic circuit with two inputs \(A\) and \(B\) and the output \(C\). The voltage waveforms across \(A, B\), and \(C\) are as given. The logic circuit gate is: [AIPMT 2012]
(a) The truth table of the given waveform is as shown in the table.
\(
\begin{array}{|c|c|c|c|}
\hline \text { Time interval } & \text { Input } A & \text { Input } B & \text { Output } C \\
\hline 0 \text { to } t_1 & 0 & 0 & 0 \\
\hline t_1 \text { to } t_2 & 1 & 0 & 1 \\
\hline t_2 \text { to } t_3 & 1 & 1 & 1 \\
\hline t_3 \text { to } t_4 & 0 & 1 & 1 \\
\hline t_4 \text { to } t_5 & 0 & 0 & 0 \\
\hline t_5 \text { to } t_6 & 1 & 0 & 1 \\
\hline >t_6 & 0 & 1 & 1 \\
\hline
\end{array}
\)
The logic circuit is OR gate.
To get output \(Y=1\) in the given circuit which of the following input will be correct? [AIPMT 2012, 2010]
\(
\begin{array}{|l|l|l|l|}
\hline & A & B & C \\
\hline a . & 1 & 0 & 1 \\
\hline b . & 1 & 1 & 0 \\
\hline c . & 0 & 1 & 0 \\
\hline d . & 1 & 0 & 0 \\
\hline
\end{array}
\)
(a) The Boolean expression of the given circuit is
\(
Y=(A+B) \cdot C
\)
From the above truth table it is clear that \(Y=1\), when \(A=1, B=0\) and \(C=1\)
The symbolic representation of four gates is shown as: [AIPMT 2011]
Pick out which ones are for AND, NAND, and NOT gates, respectively.
(c) (ii)-AND, (iii)- NOT and (iv)-NAND
If a small amount of antimony is added to germanium crystal: [AIPMT 2011]
(b) When a small amount of antimony (pentavalent) is added to germanium (tetravalent) crystal: then crystal becomes \(n\)-type semiconductor. In \(n\)-type semiconductor electrons are the majority charge carriers and the holes are the minority charge carriers.
In a forward biasing of the p-n junction: [AIPMT 2011]
(b) In forward biasing, the positive terminal of the battery is connected to \(p\)-side and the negative terminal to \(n\)-side of \(p\) – \(n\) junction. The forward bias voltage opposes the potential barrier. Due to it, the depletion region becomes thin.
A Zener diode, having a breakdown voltage equal to 15 V, is used in a voltage regulator circuit as shown in the figure. The current through the diode is: [AIPMT 2011]
(a)
The voltage drop across \(1 \mathrm{k} \Omega=V_Z=15 \mathrm{~V}\)
The current through \(1 \mathrm{k} \Omega\) is
\(
I^{\prime}=\frac{15 \mathrm{~V}}{1 \times 10^3 \Omega}=15 \times 10^{-3} \mathrm{~A}=15 \mathrm{~mA}
\)
The voltage drop across \(250 \Omega=20 \mathrm{~V}-15 \mathrm{~V}=5 \mathrm{~V}\)
The current through \(250 \Omega\) is
\(
I=\frac{5 \mathrm{~V}}{250 \Omega}=0.02 \mathrm{~A}=20 \mathrm{~mA}
\)
The current through the zener diode is
\(
I_{\mathrm{z}}=I-I^{\prime}=(20-15) \mathrm{mA}=5 \mathrm{~mA}
\)
In the following figure, the diodes which are forward biased are: [AIPMT 2011]
(c) p-n junction is said to be forward biased when \(p\) side is at a higher potential than \(n\) side. It is for circuit (a) and (c).
Pure Si at 500 K has an equal number of electron \(\left(n_e\right)\) and hole \(\left(n_h\right)\) concentrations of \(1.5 \times 10^{16} \mathrm{~m}^{-3}\). Doping by indium increases \(n_h\) to \(4.5 \times 10^{22} \mathrm{~m}^{-3}\). The doped semiconductor is of: [AIPMT 2011]
(a) \(p\)-type semiconductor is obtained when Si or Ge is doped with a trivalent impurity like aluminium ( Al ), boron ( B ), indium ( In ) etc, Here, \(n_i=1.5 \times 10^{16} \mathrm{~m}^{-3}, \quad n_h=4.5 \times 10^{22} \mathrm{~m}^{-3}\)
As we know \(n_e n_h=n_i^2\)
\(
n_e=\frac{n_i^2}{n_h}=\frac{\left(1.5 \times 10^{16} \mathrm{~m}^{-3}\right)^2}{4.5 \times 10^{22} \mathrm{~m}^{-3}}=5 \times 10^9 \mathrm{~m}^{-3}
\)
Which one of the following statements is false? [AIPMT 2010]
(b) In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers.
The following figure shows a logic gate circuit with two inputs \(A\) and \(B\), and the output \(Y\). The voltage waveforms of \(A, B\) and \(Y\) are as given. [AIPMT 2010]
The logic gate is
(c)Â It is clear from given logic circuit, that out put \(Y\) is low when both the inputs are high, otherwise it is high. Thus logic circuit is NAND gate.
\(
\begin{array}{|c|c|c|}
\hline A & B & Y \\
\hline 1 & 1 & 0 \\
\hline 0 & 0 & 1 \\
\hline 0 & 1 & 1 \\
\hline 1 & 0 & 1 \\
\hline
\end{array}
\)
A p-n photodiode is fabricated from a semiconductor with a band gap of 2.5 eV. It can detect a signal of wavelength: [AIPMT 2009]
(d) Band gap \(=2.5 \mathrm{eV}\)
The wavelength corresponding to 2.5 eV
\(\)
=\frac{12400 \mathrm{eV} Ã…}{2.5 \mathrm{eV}}=4960 Ã….
\(\)
4000 Ã… can excite this.
The p-n photodiode can detect wavelengths shorter than 4960 Ã… . Therefore, it can detect signals in the visible spectrum and some ultraviolet light.
The symbolic representation of four logic gates is as shown: [AIPMT 2009]
The logic symbols for OR, NOT, and NAND gates are respectively:
(c) (iv)-OR gate, (ii)-NOT gate, (i)-NAND gate
A p-n photodiode is made of a material with a bandgap of 2.0 eV. The minimum frequency of the radiation that can be absorbed by the material is nearly: [AIPMT 2008]
(b) Band gap \(=2 \mathrm{eV}\).
Wavelength of radiation corresponding to this energy,
\(
\lambda=\frac{h c}{E}=\frac{12400 \mathrm{eVA}}{2 \mathrm{eV}}=6200 Ã…
\)
The frequency of this radiation
\(
\begin{aligned}
= & \frac{c}{\lambda}=\frac{3 \times 10^8 \mathrm{~m} / \mathrm{s}}{6200 \times 10^{-10} \mathrm{~m} / \mathrm{s}} \\
\Rightarrow f & =5 \times 10^{14} \mathrm{~Hz} .
\end{aligned}
\)
The circuit is equivalent to: [AIPMT 2008]
(c) \(Y=\overline{\overline{\overline{A+B}}}=\overline{A+B}.\)
In the following circuit, the output \(Y\) for all possible inputs \(A\) and \(B\) is expressed by the truth table: [AIPMT 2007]
(d) \(Y=\overline{\overline{A+B}}=A+B .\)
In the energy band diagram of a material shown below, the open circles and filled circles denote holes and electrons respectively. The material is a/an: [AIPMT 2007]
(a) In this Band diagram, the number of holes in the valence band are more as compared to number of electrons in the conduction band. So, it is a p-type semiconductor.
Which of the following is an example of forward biasing? [AIPMT 2006]
(d) For forward bias p-side should be positive with respect to n-side. Option (d) satisfies this condition.
The following figure shows a logic gate circuit with two inputs A and B and the output C. The voltage waveforms of \(\mathrm{A}, \mathrm{B}\), and \(\mathrm{C}\) are as shown below: [AIPMT 2006]
The logic circuit gate is:
(a) The truth table corresponding to waveform is given by
\(
\begin{array}{|l|l|l|}
\hline A & B & C \\
\hline 1 & 1 & 1 \\
\hline 0 & 1 & 0 \\
\hline 1 & 0 & 0 \\
\hline 0 & 0 & 0 \\
\hline
\end{array}
\)
\(\therefore\) The given logic circuit gate is AND gate.
Application of a forward bias to a p-n junction: [AIPMT 2005]
(b) When \(p\)-side of junction diode is connected to positive of battery and \(n\)-side to the negative, then junction diode is forward biased. In this condition, more number of electrons enter in \(n\)-side from battery, thereby increasing the number of donor on \(n\)-side.
Carbon, Silicon, and Germanium atoms have four valence electrons each. Their valence and conduction bands are separated by energy band gaps represented by \(\left(\mathrm{E}_{\mathrm{g}}\right)_{\mathrm{C}},\left(\mathrm{E}_{\mathrm{g}}\right)_{\mathrm{Si}^{\prime}}\), and \(\left(\mathrm{E}_{\mathrm{g}}\right)_{\mathrm{Ge}}\) respectively. Which one of the following relationships is true in their case? [AIPMT 2005]
(b) Band gap of carbon is 5.5 eV while that of silicon is 1.1 eV.
\(
\left(E_g\right)_{\mathrm{C}}>\left(E_g\right)_{\mathrm{S}_1}
\)
Identify the incorrect statement from the following: [AIPMT 2005]
(a) In semiconductor, resistivity decreases with increase in temperature. With the increase in temperature, more and more electrons jump to the conduction band. So, conductivity increases and resistivity decreases.
Zener diode is used for: [AIPMT 2005]
(b) Zener diode is used for stabilisation while \(p-n\) junction diode is used for rectification.
In a \(p-n\) junction photo cell, the value of the photo-electromotive force produced by monochromatic light is proportional to [AIPMT 2005]
(b) In a photocell, photoelectromotive force, is the force that stimulates the emission of an electric current when photovoltaic action creates a potential difference between two points, and the electric current depends on the intensity of incident light.
The output of the OR gate is 1 : [AIPMT 2004]
(a)
\(
\begin{array}{|l|l|l|}
\hline A & B & Y \\
\hline 0 & 0 & 0 \\
0 & 1 & 1 \\
1 & 0 & 1 \\
1 & 1 & 1 \\
\hline
\end{array}
\)
From truth table we can observe that if either of input is one then output is one. Also if both the inputs are one then also output is one.
The peak voltage in the output of a half-wave diode rectifier fed with a sinusoidal signal without a filter is 10 V . The DC component of the output voltage is: [AIPMT 2004]
(a)Â Hence, we can say that the dc component of the output voltage is given by:
\(
V_{dc}=\frac{\int_0^\pi 10 \sin (\omega t)}{2 \pi}
\)
We have to put the values to get the following expression:
\(
\begin{aligned}
& =\frac{10}{2 \pi}(-\cos \theta)_0^\pi=\frac{2 \times 10}{2 \pi} \\
& =10 / \pi V
\end{aligned}
\)
So, we can say that the peak voltage in the output of a half-wave diode rectifier fed with a sinusoidal signal without filter is 10 V will have the dc component of the output voltage as \(10 / \pi ~V\).
Note: \(V_{d c}=\frac{V_{\text {peak }}}{\pi}\)
Of the diodes shown in the following diagrams, which one of the diodes is reverse biased? [AIPMT 2004]
(b) A diode is said to be reverse biased if \(p\)-type semiconductor of \(p-n\) junction is at low potential with respect to \(n\)-type semiconductor of \(p-n\) junction. It is so for circuit (b).
In semiconductors at room temperature: [AIPMT 2004]
(d) In semiconductors at room temperature the electrons get enough energy so that they are able to over come the forbidden gap. Thus at room temperature the valence band is partially empty and conduction Band is partially filled. Conduction band in semiconductor is completely empty only at 0 K.
Following diagram performs the logic function of: [AIPMT 2003]
(a) \(Y=\overline{\overline{\mathrm{A} \cdot \mathrm{~B}}}={\mathrm{A} \cdot \mathrm{~B}}\)
The barrier potential of a p-n junction diode does not depend on: [AIPMT 2003]
(a) Barrier potential of a p-n junction diode does not depend on diode design.
If a full-wave rectifier circuit is operating from 50 Hz mains, the fundamental frequency in the ripple will be: [AIPMT 2003]
(d) In a full wave rectifier, the fundamental frequency in ripple is twice of input frequency (100 Hz).
Reverse bias applied to a junction diode: [AIPMT 2003]
(b) In reverse biasing, the conduction across the \(p-n\) junction takes place due to minority carriers, therefore, the size of the depletion region (potential barrier) rises.
For the given circuit of the p-n junction diode, which of the following statements is correct? [AIPMT 2002]
(a) In forward biasing, the resistance of \(p-n\) junction diode is very low to the flow of current. So practically all the voltage will be dropped across the resistance \(R\), i.e. voltage across \(R\) will be \(V\). In reverse biasing, the resistance of \(p-n\) junction diode is very high. So the voltage drop across \(R\) is zero.
The given truth table is for which logic gate: [AIPMT 2002, 2001, 1998, 1994]
\(
\begin{array}{|c|c|c|}
\hline \mathbf{A} & \mathbf{B} & \mathbf{Y} \\
\hline \mathbf{1} & 1 & 0 \\
\hline 0 & 1 & 1 \\
\hline 1 & 0 & 1 \\
\hline 0 & 0 & 1 \\
\hline
\end{array}
\)
(a) A NAND gate’s output is a logical “0” (low) only when all its inputs are logic “1” (high). Otherwise, the output is logic “1”. It’s essentially the complement of an AND gate.
What is the correct statement regarding a p-n junction: [AIPMT 2002]
(a) On account of difference in concentration of charge carriers in the two sections of \(p-n\) junction, the electrons from \(n\) region diffuse through the junction into \(p\)-region and the holes from \(p\)-region diffuse into \(n\) region.
Since the hole is a vacancy of an electron, when an electron from \(n\) region diffuses into the \(p\)-region, the electron falls into the vacancy, i.e. it completes the covalent bond. Due to migration of charge carriers across the junction, the \(n\)-region of the junction will have its electrons neutralized by holes from the p-region, leaving only ionised donor atoms (positive charges) which are bound and cannot move. Similarly, the \(p\) region of the junction will have ionised acceptor atoms (negative charges) which are immobile.
The accumulation of electric charges of opposite polarities in the two regions of the junction gives rise to an electric field between these regions as if a fictitious battery is connected across the junction with its positive terminal connected to \(n\) region and negative terminal connected to \(p\) region. Therefores in a \(p-n\) junction high potential is at N side and low potential is at \(P\) side.
The current \((I)\) in the circuit will be: [AIPMT 2001]
(b) \(D_1 \rightarrow\) reverse biased \& \(D_2 \rightarrow\) forward biased. Equivalent circuit is
\(
I=\frac{5 \mathrm{~V}}{(30+20) \Omega}=\frac{5}{50} \mathrm{~A} .
\)
Given Truth table is correct for: [AIPMT 2000]
\(
\begin{array}{|l|l|l|}
\hline A & B & Y \\
\hline 1 & 1 & 1 \\
\hline 1 & 0 & 0 \\
\hline 0 & 1 & 0 \\
\hline 0 & 0 & 0 \\
\hline
\end{array}
\)
(b) AND gate: Output is 1 when both inputs are 1.
From the following diode circuit, which diode is in forward biased condition: [AIPMT 2000]
(a) A diode is said to be forward biased if \(p\) type semiconductor of \(p-n\) junction is at positive potential with respect to \(n\)-type semiconductor of \(p-n\) junction.
The depletion layer has (for an unbiased p-n junction): [AIPMT 1999]
(c) In an unbiased p-n junction, the depletion layer primarily consists of static ions (ionized dopant atoms). These ions, which are immobile, are left behind after charge carriers (electrons and holes) diffuse across the junction.
Zener diode is used as: [AIPMT 1999]
(c) A Zener diode can be used as a voltage regulator or voltage stabilizer to provide a constant voltage from a source whose voltage ( AC) may fluctuate over a wide range.Â
The truth table for the following network is: [AIPMT 1999]
(b) This is an EX-OR gate. The output of EX-OR is 1 when the inputs are different(A=1, B=0 or B=1 or A=0), otherwise the output is 0.
A p-n junction diode can be used as [AIPMT 1999]
(d) A p-n junction diode is primarily used as a rectifier.
Explanation:
A diode acts as a rectifier because it allows current to flow primarily in one direction (forward bias) and blocks it in the other (reverse bias). This unidirectional current flow is crucial for converting alternating current (AC) to direct current (DC).
In a \(p\) type semiconductor, the majority carriers of current are [AIPMT 1999]
(c) In a p-type semiconductor, the majority charge carriers are holes.
In an n-type semiconductor, the majority charge carriers are electrons.
In forward bias, the width of potential barrier in a \(p-n\) junction diode [AIPMT 1999]
(b) In forward biasing, the conduction across \(p-n\) junction takes place due to migrations of majority carriers (i.e. electrons from \(n\)-side to \(p\)-side and holes from \(p\)-side to \(n\)-side), hence the size of depletion region decreases.
In a junction diode, the holes are due to [AIPMT 1999]
(d) In a semiconductor, when an electron leaves its place, a positive charge is left behind and it is known as hole. Hence, holes are created becauase of missing electrons.
Which of the following, when added as an impurity into the silicon produces \(n\) type semiconductor? [AIPMT 1999]
(b) To create an n-type semiconductor, we have to dope with a pentavalent impurity (P (phosphorus) is pentavalent).
The cause of the potential barrier in a \(p-n\) diode is [AIPMT 1998]
(d) concentration of positive and negative charges near the junction.
The potential barrier in a p-n diode is created due to the diffusion of majority charge carriers (electrons from n-type to p-type and holes from p-type to n type) across the junction. This diffusion leaves behind immobile ions in the respective regions, creating a depletion region. These immobile ions, being positively or negatively charged, near the junction cause a concentration of positive and negative charges, which in turn establishes an electric field that opposes further diffusion and creates the potential barrier.
One part of a device is connected to the negative terminal of a battery and the other part is connected to the positive terminal of a battery. If their ends are now altered, current does not flow in circuit. The device is: [AIPMT 1998]
(c) On reversing the polarity of the battery, the \(p-n\) junction is reverse-biased. As a result of which its resistance becomes high, and the current through the junction drops to almost zero.
The following logic gate is: [AIPMT 1998, 1996]
(b) NAND
The following table is for which logic gate? [AIPMT 1998]
\(
\begin{array}{|c|c|c|}
\hline A & B & Y \\
\hline 0 & 0 & 1 \\
\hline 0 & 1 & 1 \\
\hline 1 & 0 & 1 \\
\hline 1 & 1 & 0 \\
\hline
\end{array}
\)
(c) The given truth table is for an NAND gate.
Which of the following gates will have an output of 1? [AIPMT 1998]
(a, d) The output of NAND and EX-NOR gate is 1.
The diode used in the circuit shown in the figure has a constant voltage drop at 0.5 V at all currents and a maximum power rating of 100 milli watts. What should be the value of the resistor \(R\), connected in series with diode for obtaining maximum current? [AIPMT 1997]
(c) Voltage drop across diode \(\left(V_D\right)=0.5 \mathrm{~V}\);
Maximum power rating of diode \((P)=100 \mathrm{~mW}\) \(=100 \times 10^{-3} \mathrm{~W}\) and source voltage \(\left(V_s\right)=1.5 \mathrm{~V}\).
The resistance of diode \(\left(R_D\right)\)
\(
=\frac{V_D^2}{P}=\frac{(0.5)^2}{100 \times 10^{-3}}=2.5 \Omega
\)
And current in diode \(\left(I_D\right)=\frac{V_D}{R_D}=\frac{0.5}{2.5}=0.2 \Omega\).
Therefore total resistance in circuit \((R)\)
\(
=\frac{V_x}{I_D}=\frac{1.5}{0.2}=7.5 \Omega .
\)
And the value of the series resistor \(=\) Total resistance of the circuit – Resistance of diode
\(
=7.5-2.5=5 \Omega \text {. }
\)
The following truth-table belongs to which one of the following four gates? [AIPMT 1997, 1995]
\(
\begin{array}{|ll|l|}
\hline A & B & Y \\
\hline 1 & 1 & 0 \\
1 & 0 & 0 \\
0 & 1 & 0 \\
0 & 0 & 1 \\
\hline
\end{array}
\)
(b) \(For NOR gate, } Y=\overline{A+B}\)
To obtain a p-type germanium semiconductor, it must be doped with [AIPMT 1997]
(a) For a \(p\) type germanium semiconductor, it must be doped with a trivalent impurity atom. Since indium is a third group members therefore germanium must be doped in indium.
When arsenic is added as an impurity to silicon, the resulting material is [AIPMT 1996]
(b) When arsenic is added as an impurity to silicon, the resulting material is \(n\) type semiconductor.
Explanation:
Arsenic has five valence electrons, while silicon has four. When arsenic is added to silicon, it forms covalent bonds with the silicon atoms, leaving one extra electron per arsenic atom free to move around. This extra electron contributes to the conductivity of the material, making it an \(n\)-type semiconductor.
In the case of forward biasing of p-n junction, which one of the following figures correctly depicts the direction of flow of carriers? [AIPMT 1995]
(a) In a conventional current flow in a Forward Biased PN Junction Diode, the current flows from the battery anode to the cathode.
In \(p\) region, the direction of the conventional current is the same as the flow of holes.
In \(n\) region direction of conventional current is opposite to the direction of the flow of electrons.
So, the figure correctly showing the conventional current inside the diode is option (a).
Which of the following, when added as an impurity, into the silicon, produces \(n\)-type semiconductor? [AIPMT 1995]
(a) Phosphorous (P) is pentavalent and silicon is tetravalent. Therefore, when silicon is doped with pentavalent impurity, it forms a n-type semiconductor.
When a \(p-n\) junction diode is reverse biased the flow of current across the junction is mainly due to [AIPMT 1994]
(b) When \(p-n\) junction is reverse biased, the flow of current is due to drifting of minority charge carriers across the junction.
In the diagram, the input is across the terminals A and C and the output is across B and D. Then the output is [1994]
(c) The given circuit is a circuit of full wave rectifier.
Diamond is very hard because [AIPMT 1993]
(b) Diamond’s exceptional hardness is primarily due to its large cohesive energy. This energy arises from the strong covalent bonds between carbon atoms, forming a rigid three-dimensional network. The large cohesive energy signifies the significant amount of energy required to break these bonds and separate the atoms, contributing to diamond’s high hardness and melting point.
A piece of copper and other of germanium are cooled from the room temperature to 80 K , then [AIPMT 1993]
(d)Â When both copper and germanium are cooled from room temperature to 80 K , the resistance of copper will decrease while the resistance of germanium will increase.
Explanation:
Copper:
As a metal, copper has a positive temperature coefficient of resistance. This means its resistance generally increases with increasing temperature. When cooled, the thermal vibrations of the atoms decrease, leading to fewer collisions between electrons and atoms, which in turn reduces resistance.
Germanium:
Germanium is a semiconductor. Semiconductors have a negative temperature coefficient of resistance. This means their resistance decreases with increasing temperature. When cooled, the number of free charge carriers (electrons and holes) decreases, leading to a lower conductivity and thus an increase in resistance.
Which one of the following is the weakest kind of the bonding in solids? [AIPMT 1992]
(c) van der Waals.
Explanation: Van der Waals forces are the weakest type of bonding because they are based on temporary, weak attractions between molecules due to fluctuations in electron distribution, making them significantly weaker than the other options.
lonic bonding: Involves the transfer of electrons between atoms, creating strong electrostatic attractions between positively and negatively charged ions.
Metallic bonding: Results from the delocalization of electrons in a metal, creating a “sea” of electrons that are attracted to the positively charged metal ions.
Covalent bonding: Involves the sharing of electrons between atoms, forming strong bonds between them.
The depletion layer in the p-n junction region is caused by [AIPMT 1991]
(b) The depletion layer in the \(p-n\) junction region is caused by diffusion of charge carriers.
The following truth table corresponds to the logical gate [AIPMT 1991]
\(
\begin{array}{lll}
A & B & Y \\
0 & 0 & 0 \\
0 & 1 & 1 \\
1 & 0 & 1 \\
1 & 1 & 1
\end{array}
\)
(b) This truth table is of identity, \(Y=A+B\), hence OR gate.
When \(n\) type semiconductor is heated [AIPMT 1989]
(d) Due to heating, when a free electron is produced than simultaneously a hole is also produced.
p-n junction is said to be forward biased, when [1988]
(a) For forward biasing of \(p-n\) junction, the positive terminal of external battery is to be connected to \(p\) semiconductor and negative terminal of battery to the \(n\) semiconductor.
At absolute zero, Si acts as [1988]
(c) At absolute zero, silicon ( Si ) acts as an insulator.
Explanation: At absolute zero, all electrons are in their lowest energy states and do not have enough energy to move into the conduction band, making them unable to conduct electricity effectively, thus behaving like an insulator.
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